The present invention relates to testing of integrated circuit (IC) chips, and more particularly to failure analysis of semiconductor IC chips. More particularly, this invention relates to an improved testing technique for testing IC chips using picosecond imaging circuit analyzer(PICA)techniques.
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Very large scale integration (VLSI) logic integrated circuit (IC) chips, e.g. microprocessors, contain very large numbers of logic circuits. Testing the many logic circuits in a chip is an important part of the manufacturing process of the chip.
Logic circuits typically include many interconnected logic gates. The various logic gates include, e.g., xe2x80x9cANDxe2x80x9d gates, xe2x80x9cORxe2x80x9d gates, xe2x80x9cNANDxe2x80x9d gates, xe2x80x9cNORxe2x80x9d gates, xe2x80x9cNOTxe2x80x9d gates, xe2x80x9cXORxe2x80x9d gates and so on. A logic circuit has a number of inputs for receiving data, and a number of outputs for outputting data. The logic circuit is designed such that for each input pattern, of a set of one or more input patterns, provided at the inputs of the logic circuit, a corresponding predetermined output pattern is produced at the outputs of the circuit.
If there is a fault or defect in the logic circuit, then for one or more input patterns provided at the inputs of the circuit, the observed output patterns produced at the outputs of the circuit will differ from the expected predetermined output patterns.
One way to test for faults in a logic circuit is to apply each possible input pattern at the inputs of the logic circuit, and to compare the actual output pattern with the expected output pattern. For small numbers of possible input patterns, the cost of storing the expected output patterns and performing this deterministic testing is reasonable. However, for large numbers of possible input patterns, the cost of such deterministic testing is too high.
An alternative method of testing for faults in a logic circuit applies random input test patterns at the inputs of the logic circuit, and compares the actual output patterns with the expected output patterns. The number of random test patterns needed to achieve a selected level of confidence that a logic circuit contains no faults depends on the circuit design.
Another alternative method of testing for faults in a logic circuit applies one or more weighted random input test patterns at the inputs of a logic circuit, and compares the actual output patterns with the expected output patterns. The weights may be uniform across all digits in the test pattern, or the weights may be nonuniform. The weighted random test patterns are selected to achieve, efficiently and at a low cost, a desired level of confidence that the logic circuit contains no faults.
As integrated circuit chip devices have become more densely packed with electronic components and more complex, the need for effectively testing such circuits has become more important. This is especially true of digital logic circuits. In order to provide a mechanism for testing complex circuitry of this type, a number of built-in self test (BIST) methodologies have been employed including level sensitive scan design (LSSD) techniques. LSSD design can be performed in accordance with the teachings of xe2x80x9cLevel Sensitive Logic System,xe2x80x9d U.S. Pat. No. 3,783,254, and xe2x80x9cMethod of Level Sensitive Testing A Functional Logic System,xe2x80x9d U.S. Pat. No. 3,761,695, both to Edward B. Eichelberger and of common assignee to this invention, the contents of which are incorporated herein by reference in their entireties.
In the LSSD methodology, a long string of shift register latches (SRLs) is employed in a dual function role which does not detract from normal circuit operation. In particular, a shift register (SR) string provides normal input during circuit operation and provides a mechanism for providing test input signals to the circuit for testing purposes. These tests may be employed, for example, immediately subsequent to chip manufacture, and in field test error conditions. Depending on the source of input signals to the SRL scan string, either normal operations or test operations can be carried out.
An important concept for grasping the present invention, is the notion of a xe2x80x9ccone of logic.xe2x80x9d In any given logic circuit, there are input and output signal lines. Not every input line can generally influence every output signal line. Conversely, each output signal line is generally capable of being influenced only by a subset of input signal lines. Thus, each output signal line is associated with a cone of logic representing signal paths through which input signals influence the output signal. Furthermore, an input signal line can influence the output at more than one output signal line. Thus, one can associate with each output signal line a subset of input signal lines passing through and defining the cone of logic. One can associate with each input signal line a subset of output signal lines which can be influenced by the input signal present on any selected input signal line. For further discussion of logic cones, the reader is referred to xe2x80x9cDelay Test Coverage Enhancement for Logic Circuitry Employing Level Sensitive Scan Design,xe2x80x9d U.S. Pat. No. 5,278,842, to Edward B. Eichelberger of common assignee to this invention, the contents of which is incorporated herein by reference in its entirety.
An example testing technique of VLSI logic chips, i.e. microprocessors, using pseudo-random pattern generation techniques, is logic built-in self test (LBIST). LBIST initializes a set of latches and generates a set of pseudo-random latch value patterns for all latches in a chip. A clock pulse scans the test pattern and the output is then compared to an expected result. Thereafter, a new set of latch values can be loaded into the latches. For further information regarding LBIST techniques, the reader is referred to xe2x80x9cSelf-Testing of Multichip Modules,xe2x80x9d by P. H. Bardell and W.H. McAnney, in Proceedings of the IEEE International Test Conference, 1982, pages 200-204, the contents of which is incorporated herein by reference in its entirety.
Weighted random pattern (WRP) testing uses circuitry added to a pseudo-random number generator to weight the inputs to the device under test to produce a greater number of ones or zeros. WRP is described at length in xe2x80x9cWeighted Random Pattern Testing Apparatus and Method,xe2x80x9d U.S. Pat. No. 4,688,223, to Franco Motika and John A. Waicukauski, of common assignee to this invention, the contents of which is incorporated herein by reference in its entirety.
A new circuit testing technique called picosecond imaging circuit analyzer (PICA) captures weak, transient light pulses that are emitted by individual switching transistors through the backside of the chip. Airline passengers on a night flight can see the traffic of cities beneath them traced out by illumination from vehicles"" headlights. In much the same way, chip designers using PICA can use light emitted by speeding electrons to examine the activity of circuits in computer chips. Electronic engineers can use PICA to spot problems in their circuit designs and manufacturing processes, and to debug chips.
Scientists have known since the 1980s that electrons emit light known as photons when they speed through field effect transistors (FETs), the building blocks of complementary metal-oxide-semiconductor (CMOS) microchips. Microprocessors and memory chips can be made from CMOS circuits. The electrons move only when the CMOS circuits change from one state to another, switching on or off. Detecting these very faint light emissions can be used to monitor the switching of individual components of advanced CMOS chips.
High-speed optical detectors can be used to monitor light emissions from simple high-speed circuits. A sophisticated detector can permit imaging and time-resolving light emission from hundreds or thousands of devices on a chip simultaneously. The PICA technique produces xe2x80x9cmoviesxe2x80x9d of information flowing through complex chips, such as microprocessors. The technique was named picosecond imaging circuit analysis because the pulses of light last for only picoseconds (trillionths of a second).
PICA technology led to a semiconductor testing tool with application in spotting and diagnosing faults in chips at the design and prototyping level.
PICA is a method for recording time and location of photon emission. PICA can be used for chip characterization including timing and clock skew. PICA can also be used for failure analysis such as for DC and timing fails. Few photons are generated per switch so a high repetition rate is needed for practicality. Thus, PICA can only be used today practically for clocking and scanning.
Chip innovations include increasing speed, decreasing size and new packaging styles. These innovations drive changes in the technologies needed to test and debug the chips. Such tests are critical for identifying failures and faults in chip designs and manufacturing.
One chip innovation involves wires that connect individual transistors. In earlier generations of chips, one or two layers of wiring connected the transistors, so that most of the transistors and wires were directly visible. More recently, however, the wiring on the chip is much more complex, leading to as many as seven levels of wiring. Bottom layers of wires and the transistors are often almost completely covered by the upper layers of wires. As a result, traditional methods of measuring electrical activity on a chip are becoming impractical. PICA can overcome this because it can look at the transistors through the backside of a chip, where no metal wires get in the way.
The reader is referred to the following documents further describing PICA techniques, J. C. Tsang and J. A. Kash, xe2x80x9cPicosecond hot electron light emission from submicron complementary metal-oxide semiconductor circuits,xe2x80x9d Applied Physics Letters, Vol. 70, No. 7, Feb. 17, 1997, pages 889-891, J. A. Kash, J. C. Tsang, xe2x80x9cDynamic Internal Testing of CMOS Circuits using Hot Luminescence,xe2x80x9d IEEE Electron Device Letters, Vol. 18, 1997, pages 330-332, Dave Vallett, Dr. Jeff Kash, and Dr. Jim Tsang, xe2x80x9cWatching Chips Work,xe2x80x9d MicroNews, Vol. 4, No. 1, First Quarter 1998, pages 23-25, J. A. Kash, J. C. Tsang, Richard F. Rizzolo, Atul K. Patel, and Aaron D. Shore, xe2x80x9cBackside Optical Emission Diagnostics for Excess IDDQ,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol. 33, No. 3, March 1998, pages 508-511, and D. Knebel, P. Sandra, D. Vallet, L. Huisman, P. Nigh, R. Rizzolo, P. Song, and F. Motika, xe2x80x9cDiagnosis and Characterization of Timing-Related Defects by Time-Dependent Light Emission,xe2x80x9d Proceedings of 1998 IEEE International Test Conference, October 1998, pages 733-739, the contents of which are incorporated herein by reference in their entirety.
Unfortunately, PICA cannot conventionally be used in certain testing situations because the weak, transient light pulses of the circuits of the chips are undetectable. For example, LBIST and WRP test techniques cannot use PICA. PICA techniques require high repetition rates of specific test patterns in order to get a sufficiently good image. Test patterns that have worked well with PICA are clocking patterns and scan patterns, both of which have high repetition rates. Conventional standard chip test techniques such as LBIST and WRP do not have high repetition rates. Thousands of clocks must be applied to fully load a scan chain for each test pattern and only one clock may cause a fail in 100 or more patterns. The duty cycle can easily be less than 1/100,000. A circuit that fails during an LBIST or WRP test is simply not stimulated often enough to provide a PICA image. Therefore PICA, a valuable testing technique, can not presently be used for detecting LBIST and WRP fails.
What is needed then is a technique enabling sufficient exercise of LBIST and WRP failing chip circuits to permit identification using PICA testing techniques.
The present invention includes a method and system for testing integrated circuit chips, including the steps of performing a binary search to a first failing pattern, determining a failing sink latch, performing a back cone trace to determine all source latches, determining source latch logic states, positioning the source latch logic states in a scan chain, exercising a chip scan path by applying logic transitions on the source latches in the absence of a system L1 clock, generation of a synchronization signal to increase signal-to-noise ratio, and observing an exercised failing circuit.
In an embodiment of the invention, the method includes the steps of using PICA techniques to observe the exercised failing circuit.
In another embodiment of the invention, the method includes using at least one of an LBIST and a WRP technique to search for the failing pattern.
In yet another embodiment of the invention, the method includes the step of using an algorithm to exercise the failing circuit.
In yet another embodiment of the invention, the method includes the step of creating a net pattern to be scanned including a sum of an original pattern causing a failing circuit to be exercised, and one or more shifted versions of the original pattern.
In another embodiment of the invention, the algorithm can include a step where one of the shifted versions is shifted a number of clocks wherein the number of clocks is equal to the length of the original pattern.
In yet another embodiment of the invention, the algorithm can include step where one of the shifted versions is shifted a number of clocks, wherein the number of clocks is chosen so that the sum of the original pattern and the one of the shifted versions does not cause a scan conflict.
In another embodiment of the invention, the method further includes the step of using an algorithm to densify the pattern set.
In yet another embodiment of the invention, a synchonization or xe2x80x9cshutter openxe2x80x9d signal can be generated and provide a means for capturing only desired transitions with the PICA imaging system, increasing the signal-to-noise ratio.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings.